Integrated semiconductor circuits or devices are designed and used for widely differing applications. It often is not cost effective to create separate fabrication lines, with different masks and such, for each small change for various applications. As such, the device is personalized to meet various needs by opening and closing links using various techniques.
One technique for opening a previously closed link involves fuses. The appropriate fuses are blown by a laser or other means to personalize the semiconductor circuit or device. One technique for closing a previously opened link involves antifuses. Antifuses are structures that, when first fabricated, are an open circuit. When the antifuse is “fused,” the open circuit becomes closed and conduction across the antifuse becomes possible. Thus, antifuses are used to perform the opposite function of a fuse.
An antifuse structure includes two electrodes separated by a dielectric. Typically an antifuse is fused by applying a sufficient voltage, called a “fusing voltage,” across the antifuse structure. This voltage causes a current to flow and the structure to fuse together, and results in a permanent electrical connection. Conventional antifuse structures include a thin layer of dielectric material between two interlevel metallic interconnection layers. The dielectric material is positioned either above or below an interconnecting via-contact between the metal interconnection levels. Conventional dielectric materials include a thin oxide (SiO2), a thin nitride (Si3N4), a thin amorphous silicon film (a-Si) or a thin composite film of oxide-nitride-oxide (ONO). Each antifuse is in appropriate electrical contact to a specific random logic node of the ALD or FPGA device to be programmed to alter a specific logic state using a programming voltage pulse of desired amplitude and time.
The semiconductor industry continuously strives to reduce the size and cost of integrated circuits. As such, there has been progressive scaling of feature size and power (Vdd). The drive to lower Vdd requires a reduced programming voltage, and requires scaling of the dielectric material of the antifuse. Conventional antifuse devices are fused using high programming voltage pulses as much as 2.5 to 3.0 times the power supply voltage (e.g. 8V to 10V for a Vdd=3.3V). This high voltage requires complex circuits for generating the high programming voltage on-chip as well as complex processing for routing such high voltages across the chip in an integrated circuit that is otherwise scaled for low voltage. Therefore, it is highly desirable to develop an antifuse technology in which the programming voltage for fusing the antifuse scales with the power supply voltage, and preferably below 2×Vdd such that simple circuits are capable of generating this lower programming voltage on-chip.
An antifuse with a thinner dielectric has a reduced programming voltage but a larger capacitance because the capacitance of a dielectric is inversely proportional to the thickness of the dielectric. One particular problem confronting the semiconductor industry is the challenge of reducing antifuse capacitance to enhance programming performance while lowering the programming voltage for Field Programmable Gate Arrays (FPGAs) and Alterable Logic Devices (ALDs). As fabricated, the structure of antifuses is electrically “open” such that it is characterized as being nonconductive and capacitive. This capacitive component of antifuses contributes significantly to the signal transmission delay of FPGA or ALD devices. Thinner oxide provides each antifuse with a higher capacitance, which results in a slower device performance. The increased capacitive components of the antifuses increase RC components, which increases logic delays and adversely affects the performance of the FPGA or ALD devices.
One known antifuse structure includes a composite of silicon-rich-nitride (SRN) and oxide (SiO2) films. These films will be described in more detail below. An effective programming pulse for this antifuse structure approaches 2×Vdd for a Vdd=3.3V. One limitation of these films is the thickness and scalability of the SiO2 layer, and the associated parasitic capacitance. The oxide thickness does not scale proportionately with the scaling of the technology and power supply generations because the antifuse device leakage in the open state is not acceptable.
Therefore, there is a need in the art to provide a scalable high performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that the programming pulse voltage is scalable with Vdd and the capacitance is lowered so as to improve circuit performance at low power.